1. Field of the Invention
The present invention generally relates to the generation of pixel clock and phase control thereof used for image forming apparatuses, and particularly, to a pixel clock generation circuit that realizes highly accurate phase control of the pixel clock and a image forming apparatus using the same.
2. Description of the Related Art
The general construction of an image forming apparatus such as a laser printer and a digital copier is shown in FIG. 40. As shown in FIG. 40, a laser beam emitted by a semiconductor laser unit 4001 is scanned by a rotating polygon mirror 4002, converges into a light spot on a photosensitive unit 4004 via a scan lens 4003, and exposes the photosensitive unit 4004 thereby to form a electrostatic latent image. Each scanned laser beam is detected by a photo detector 4005. A clock generation circuit 4008 provides clock to a phase sync circuit 4009, and the phase sync circuit 4009 generates image clock (pixel clock) in synchronization with the output signal from the photo detector 4005. The image clock is fed to a image processing unit 4006 and a laser drive circuit 4007. According to the above arrangements, the semiconductor laser unit 4001 controls a time interval in which the semiconductor laser emits a laser beam in accordance with image data generated by the image processing unit 4006 and image clock the phase of which is set by the phase sync circuit 4009 line by line thereby to control electrostatic latent image formed on the photosensitive unit 4004.
In such an scanning optical system, the speed at which a light spot scans the surface of the photosensitive unit 4004 may vary in dependence on the distance of a reflective surface of a deflection unit such as a polygon scanner from the rotative axis thereof. This change in scanning speed may cause the fluctuation of images, and results in the degradation of image quality. The scanning speed needs to be adjusted for improving image quality.
In the case of a multi-beam optical system, the frequencies of light beams may be different. If the chromatic aberration of the multi-beam optical system is not adjusted, the difference in frequencies may cause the positions of formed electrostatic latent images. This means that the range on the surface of the photosensitive unit 4004 in which each light spot scans may differ from each other, and results in the degradation of image quality. Therefore, the scan range needs to be adjusted.
These adjustments are conventionally done by changing the frequency of pixel clock thereby to control the position of the light spot along a scan line. This technique is described in a reference documents 1 and 2 described below, for example. However, the adjustment of the pixel clock frequency generally requires a complex pixel clock control unit. The smaller the quantity of frequency needs to be changed, the more complex the pixel clock control unit becomes. As a result, the fine adjustment of pixel clock frequency is difficult.
To solve this problem, the applicant has proposed in a reference document 3 (described below) a pixel clock generation circuit that can adjust the phase of the pixel clock, and the structure thereof is relatively simple. This pixel clock generation circuit basically includes a high frequency clock generation unit and a pixel clock generation unit. The high frequency clock generation unit generates a high frequency clock. The pixel clock generation unit generates a pixel clock based on the high frequency clock output from the high frequency clock generation unit and phase data indicating the transition timing of the pixel clock, and change the cycle of the pixel clock. The pixel clock generation unit includes a counter unit that counts the high frequency clock, a comparator unit that compares the count of the counter unit with the phase data indicating the transition timing of the pixel clock, and a pixel clock control unit that causes the pixel clock to make a transition based on the result of comparison performed by the comparator unit. Therefore, the pixel clock generation circuit described above still remains relatively complex.
The above reference documents are the following Japanese Patent Laid-Open Patent Applications: (1) No. 11-167081, (2) No. 2001-228415, and (3) No. 2003-098465.